Pentium FDIV bug - Pentium FDIV bug On October 30, 1994, Professor Thomas Nicely of Lynchburg College reported a bug in the Pentium floating point unit. He reported that certain division operations returned a value which was wrong by a very small amount. This result was quickly verified by other people around the Internet, and became known as the Pentium FDIV bug (FDIV is the x86 assembly language instruction for floating point division). Other people found division problems where the result returned by the Pentium was off by up to 61 parts per million. Note that this problem occurred only on some models of the original Pentium processor. Any Pentium family processor with a clock speed greater than 100 MHz is new enough not to have this bug. This report.
Pentium - Pentium The Pentium is an x86 architecture microprocessor by Intel which first shipped on March 22, 1993. It is the successor to the 486 line. The Pentium was originally to be named 80586 or i586, but the name was changed to Pentium because numbers could not be trademarked. Major changes from the 486: Superscalar architecture - The Pentium has two datapaths that allow it to complete more than one instruction per clock cycle. One pipe (called "U") can handle any instruction, while the other (called "V") can handle the simplest, most common instructions. 64-bit data path - This doubles the amount of information pulled from the memory on each fetch. MMX instructions (later models only) - Special 64-bit functions designed for use in multimedia applications. Pentium.
Pentium 4 - Pentium 4 The Pentium 4 is an x86 architecture microprocessor by Intel, their first all-new CPU design since the Pentium Pro of 1995. The original Pentium 4, codenamed "Willamette", ran at 1.4 and 1.5 GHz and was released in November 2000. Unlike the Pentium II, the Pentium III, and the various Celerons, it owed nothing to the Pentium Pro design, and was new from the ground up. To the surprise of most observers, the Pentium 4 did not improve on the old P6 design in either of the normal two key performance measures: integer processing speed or floating-point performance: instead, it sacrificed orthodox performance in order to gain two things: very high clockspeeds, and SSE performance. As is traditional with Intel's flagship chips, the P4 also.
Pentium II - Pentium II The Pentium II is an x86 architecture microprocessor by Intel, introduced in February 1997. It was based on a modifed version of the P6 core first used for the Pentium Pro, but with improved 16-bit performance and the addition of the MMX instructions which had already been introduced on the Pentium MMX. The original Klamath Pentium IIs produced an (for that time) incredible amount of heat. This was because of the 0.35µm fabrication process. They also worked with a 66MHz front side bus, which was a speed that was inadequate for the CPU's design to show its full potential. The Deschutes core Pentium IIs which debued in 1998 were produced on a more suitable 0.25µm fabrication process, meaning they ran significantly cooler. Support for.
Pentium III - Pentium III The Pentium III is an x86 architecture microprocessor by Intel, introduced in February 1999. It is very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions. The original version, Katmai was pretty much the same as the Pentium II, the only differences being the introduction of SSE, and an improved L1 cache controller (which was the cause of the minor performance improvements over the latter PIIs). The second version, Coppermine, had an integrated 256k L2 cache, which greatly improved performance over Katmai. It was built on a 0.18 micron process. It topped out at 1GHz. A 1.13GHz version was produced, but recalled after it proved to be so unstable that it was unusable. Ironically, the problem was.
Pentium Pro - Pentium Pro The Pentium Pro is an x86 architecture microprocessor by Intel originally intended to replace the Pentium Classic in a full range of applications, but later reduced to a more narrow role as a server and high-end desktop chip. It was introduced using an enormous rectangular Socket 8 form factor in November 1995. Intel has since discontinued it in favour of the newer high-end Xeon processor lines. Despite the name, the Pentium Pro is architecturely quite different from Intel's earlier Pentium processor, being based on the then-new P6 core (which in a modified form would later be used for the Pentium II and Pentium III). The P6 core features out-of-order execution, speculative execution and an additional pipe for simple instructions. Speculative execution - the provisional.
Pentium OverDrive - Pentium OverDrive The Pentium OverDrive (code-name P24T) was an Intel Pentium processor for 486 Socket 3 and Socket 2 PC motherboards. Pentium OverDrives were unlike 'normal' Pentium processors, which were designed to function with a fast 66 MHz or 60 MHz front side bus (apart from the 75 MHz version) as well as cpu sockets which did not appear on 486 motherboards. The Pentium OverDrive was provided as a means to give a Pentium-performance-level upgrade option for owners of 486 computer systems. It was however, criticised for being more expensive and slower than competing CPU-upgrade options such as the AMD Am5x86 and Cyrix Cx5x86, and being too late to the market. To perform properly, the chips were dependent on sizable amounts of secondary cache ram being.
Pentium M - Pentium M Introduced in March 2003, the Pentium M is an x86 architecture microprocessor designed and manufactured by Intel. The processor is designed for use in laptop personal computers. It was codenamed "Banias" before its introduction. The Pentium M represents a radical departure for Intel, as it is not a low-power version of the desktop-oriented Pentium 4, but instead a heavily modified version of the Pentium III design (itself a modified form of the Pentium Pro. It is optimised for power efficiency, a vital characteristic for extending notebook computer battery life. Running with very low average power consumption and much less heat output than desktop processors, the Pentium M runs at a lower clock speed than the contemporary Pentium 4 desktop processor series, but with similar.
VESA Local Bus - solution to the problem of ISA's limited bandwidth, and had several flaws that limited its useful life substantially: 80486 dependence. The VESA Local Bus relied heavily on the 80486's memory bus design. When the Pentium processor started to gain mass acceptance, circa 1995, there were major differences in its bus design, and the VESA bus was not easily adaptable. This also made moving the bus to non-Intel architectures nearly impossible. Limited number of slots available. Most PCs that used VESA Local Bus had only one or two slots available, as opposed to 5 or 6 ISA slots. This was because, as a direct branch of the 80486 memory bus, the VESA Local Bus didn't have the electrical ability to drive more than 1 or 2 cards at a time. Reliability problems..
Klamath - county which no longer exists) Klamath Falls, Oregon The Klamath River Klamath was the pre-release "code name" for Intel's Pentium II microprocessor. This article (or an earlier version of it) contains material from FOLDOC, used with permission..
IA-32 - generation of CPUs since has added several features to this set: The 80386 could accept an optional external coprocessor chip called the 80387 that enabled it to do floating point calculations via hardware. Some models of the 80486 had this coprocessor on-die. Pentium MMX added a set of extensions called MMX that can be used, among other things, to optimize multimedia software running on it. Pentium III adding SSE (Streaming SIMD Extensions) Pentium 4 adding SSE2 The 80386 has eight 32 bit general application registers (and LOTS of system controlling registers) data registers All of the four following registers may be used as general purpose registers. However each has some specialized purpose as well. eax (with a special interpretation for arithmetic instructions; a for accumulator) ebx (base register, used for addressing).
IA-64 - against the practice of assembly programming on Itanium, in general, and instead use their C++ compiler (which contains platform specific heuristics.) In order to support IA-32, the Itanium can switch into 32-bit mode with special jump escape instructions, and then return in an analogous way. The IA-32 instructions have been mapped to the Itanium's functional units. However, since the Itanium is built primarily for speed of its EPIC-style instructions, and because it has not out-of-order execution capabilities, the IA-32 instructions execute at a severe performance penalty compared to either the IA-64 mode, or its Pentium line of processors. For example, the Itanium functional units do not automatically generate integer flags as a side effect of ordinary ALU computation, and does not intrinsically support multiple outstanding unaligned memory loads. There have been.
IBM POWER - 64-bit implementation, while remaining completely compatible with the POWER instruction set. This had been one of the goals of the PowerPC project and the POWER3 was the first of the IBM processors to take advantage of it. It also added a third ALU and a second instruction decoder, for a total of eight functional units. The latest implementation is the POWER4 series which places two complete CPU cores (otherwise similar to the POWER3) on a single chip, speeds it up, and adds high-speed connections to up to three other pairs of POWER4 CPUs. They can be placed together on a motherboard to produce an 8-cpu SMP building block. When processing requires high throughput instead of high code complexity, one of a pair of cores can be turned off so that the.
Intel 80386 - Before that time, personal computers based on Intel processors were almost exclusively driven by the DOS and CP/M systems. Because of the lack of an MMU there was little point in building a file structure on pre 386 computers that differentiated between executable code and data. The inability to differentiate between executable code and data is the primary reason why computers can be infected by viruses. Intel later introduced the 80486, but neither it nor its successors under the Pentium name were as big a step as the 32-bit flat addressing made possible by the 80386. Most applications running on personal computers in 2003 will run on the older 80386, albeit very slowly; there are only a few instructions added to the main instruction set in later generations, and in most.
Intel 80486 - or voltage handling abilities from 'standard' chips of the same speed stepping. Intel 80486DX4 - designed to run at triple clock rate (not quadruple as often believed). External clock rates include 16MHz, 20MHz, 25MHz, 33MHz, 40MHz and 50MHz. Some 486 motherboards provided unofficial and undocumented support for 60 and 66MHz, however. The 486 processor has been licensed or reverse engineered by other companies such as IBM, Texas Instruments, AMD, Cyrix, and Chips & Technologies. Some are almost exact duplicates in specifications and performance, some aren't. The successor to the 486 is the Pentium processor. See also List of Intel microprocessors.
Instruction set - "Instruction set architecture" is sometimes used to distinguish this set of characteristics from the Micro-Architecture, which are the elements and techniques used to implement the ISA, e.g. microcode, pipelining, cache systems, etc. Computers with different internal designs can share a common instruction set, e.g. the Intel Pentium and the AMD Athlon both implement nearly identical versions of the x86 instruction set, but have radically different internal designs. When designing processor cores, Register Transfer Language RTL is used to define the operation of each Instruction of an Instruction Set. Some examples of ISAs: MIPS Motorola 6800 ARM PowerPC x86 (Pentium) See also: CISC, RISC, VLIW, computer architecture, emulator, RTL.
Intel i860 - lack of any solution to quickly handle context switching. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and need them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second, an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU. At first the i860 was only used in a small number of very large machines like the iPSC/860 at Los Alamos National Laboratory. As the compilers improved, the general performance of the i860 did likewise, but by that point most other RISC designs had already passed the i860 in performance. The i860 did see some use in the workstation world as.
VIA C3 - very little heat for a PC processor, and therefore can be run without a cooling fan if it is underclocked or if it has got a suitable heatsink It runs on older Socket 370 motherboards According to VIA, the VIA C3 is to be superseded in 2003 by the VIA C4 - a clone of the design of the Intel Pentium 4 processor..
Instructions Per Clock - IPC and a relatively low clock speed (like the AMD Athlon, HP PA-RISC, SUN SPARC ULTRASPARC), or from a low IPC and higher clock speed (like the Intel Pentium 4 and DEC Alpha). High-IPC, low-clock speed processor designs are traditionally called braniac designs, while low-IPC, high-clock speed are often called speed-demons. Both of them are valid processor design techniques, and the choice between the two is often dictated by engineering constraints, marketing pressures, etc. In particular, the speed-demon design of the Intel Pentium 4 is often cited by AMD fans as "cheating", since the higher clock speed rating makes the processor appear faster to the general, non-expert audience. It is suspected that this is the real reason of AMD PR-rating scheme, where the name of each processor is not equal to.
Instruction pipeline - than in the non-pipelined case. The key to understanding the advantage of pipelining is to consider what happens when this ADD instruction is "half-way done", at the ADD instruction for instance. At this point the circuitry responsible for loading data from memory is no longer being used, and would normally sit idle. In this case the pipeline controller fetches the next instruction from memory, and starts loading the data it needs into registers. That way when the ADD instruction is complete, the data needed for the next ADD is already loaded and ready to go. If the cost of accessing memory is high (which it is on modern machines), the overall effective speed of the machine can be greatly increased because no parts of the CPU sit idle. Each of the.
